Future Computer Hardware

Lecture series (LSF)

  • Invited speakers
  • Friday, 15:15 - 16:15
  • Heidelberg, INF 350 / OMZ R U014 (side entrance, basement floor)
  • 06.12.2019 - 07.02.2020

Description

The Institute of Computer Engineering (ZITI) at Heidelberg University organizes the lecture series Future Computer Hardware to illuminate the current and future hardware developments from different perspectives. Invited experts present their visions on the challenges and opportunities of new hardware designs.

Presentations

 

  • 17.02.2020 HITS Kolloquium, 11:00 Studio Villa Bosch, HITS

 

Presentations with abstracts

  • 06.12.2019 Introduction to the series with the recorded keynote from Hot Chips 2019
    • What Will the Next Node Offer Us?
    • Dr. Philip Wong, VP Corporate Research, TSMC
       
    • The power-performance-area (and cost) advances in the last five decades have mostly been achieved through dimensional scaling of the transistor. What will the semiconductor industry do after dimensional scaling of the silicon transistor crosses the nanometer threshold, from 16/12 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, 1.4 nm to sizes below a nanometer? Will these advanced logic technologies continue to provide the energy efficiency required of future computing systems? Will new applications and computation workloads demand new device technologies and their integration into future systems? These are some of the most pressing questions facing the semiconductor industry today.
       
      The path for IC technology development going forward is no longer a straight line. The need for out-of-the-box solutions ushers in a golden age of innovation. I will give an overview of the memory and logic device innovations that are in the research pipeline today. Future electronic systems require co-innovation of the computing architecture and device technology. I will speculate on how they will be integrated into future electronic systems.

       

  • 13.12.2019
    • AI needs HW - Scoping Hardware Architectures for Modern-Day Applications
    • Prof. Dr. Tobias Gemmeke, RWTH Aachen
       
    • Advances in computing performance is facing critical limitations such as the memory wall, energy consumption, or end of Moore’s law. At the same time, data scientists have abundant data at their disposal. Classic concepts re-emerge in the light of modern-day applications as hidden treasures. With more than 60 years of tremendous advances in technology, hardware architecture und algorithm design, researchers in various disciplines face anew a very exciting and disruptive time.
       
      From the perspective of a digital designer, this talk touches on a variety of recent concepts bounded by technology scaling and hardware architecture. With the prevailing lack of a crystal ball, relating to the requirements of neural networks shall provide indication of their future potential.

       

  • 10.01.2020
    • Potential Impact of Disruptive Technologies on Future Computing Systems
    • Prof. Dr. Theo Ungerer, Universität Augsburg
       
    • The EUROLAB4HPC project aims to drive Europe to become a world leader in HPC systems. EUROLAB4HPC has sponsored long-term roadmapping to promote the competitiveness of European HPC, by releasing and widely disseminating the EUROLAB4HPC Vision, which identifies technological opportunities and hurdles with a 10 to 15-year perspective.
       
      EUROLAB4HPC’s 2017 Vision foresees radical changes in computing over the decade to 2030. Because of the long-term perspective and the unavoidably speculative nature, the authors started with an assessment of computing technologies that could influence future HPC hardware and software. Enhancements of existing technologies and new inventions are expected to take place in different periods of time: in the short term, sustaining technologies will further advance, while disruptive technologies and alternative ways of computing are expected in the medium term. In the long term, new technologies may replace CMOS in processor logic and hardware acccelerators. We expect scientific and engineering applications to continuously scale well beyond Exascale computers. In addition, new applications and software technology will perform a pull on next-decade HPC, e.g. high-performance data analysis (HPDA), machine learning, and the internet of things.
       
      The talk gives an overview about the roadmapping efforts and the assessed technologies. The current Eurolab4HPC Vision (version 2017) is available at https://www.eurolab4hpc.eu/vision/. The new Vision will replace the current version in January 2020.

       

  • 17.01.2020
    • In-Memory Computing mit Memristoren
    • Prof. Dr. Dietmar Fey, Universität Erlangen-Nürnberg
       
    • Nicht-flüchtige Speicherelemente wie Resistive RAMs (ReRAMs), Phase Change Memories (PCMs), Spin-torque Magnetic RAMS (STT-MRAMs) oder Bauelemente mit ferroelektrischen Tunnelübergängen (FTJ) gehören gemäß der Systemtheorie von Leon Chua zu der Klasse der sog. Memristoren, welche neben Widerstand, Kondensator und Spule ein weiteres Basiselement der Elektronik darstellen. Gegenüber flüchtigen Speicherelementen wie SRAMs oder DRAMs zeichnen sich Memristoren durch einen niedrigen Energiebedarf beim Auslesen der Speicherinhalte, geringen Platzbedarf, der Nicht-Flüchtigkeit der in ihnen gespeicherten Speicherzustände und einer Multibit-Fähigkeit aus, d.h. es können mehr als zwei Zustände in einer physikalischen Speicherzelle gespeichert werden.
       
      Memristoren können jedoch nicht nur zum Speichern, sondern auch für das Verarbeiten von Information genutzt werden. In diesem Sinne sind Memristoren prädestiniert für neuartige Prozessor- und Rechnerarchitekturkonzepte wie In-memory-Computing, in denen das Spei-cherelement ein inhärenter Bestandteil des Verarbeitungsprozesses wird. Dies kann sowohl für analoge neuromorphische Architekturen als auch digitale Logik eingesetzt werden.
       
      Im Vortrag werden neue Konzepte vorgestellt und bewertet, wie Memristoren für neurartige rekonfigurierbare Boolesche Logik eingesetzt werden können, in der ein und dasselbe Bauteil in Abhängigkeit von Kontrollsignalen unterschiedliche Boolesche Funktionen realisiert. Ferner wird die Multibit-Fähigkeit der Memristoren für den Aufbau eines ternäres Rechenwerks zur Realisierung einer übertragsfreien Addition und für die Realisierung von Multibit-Caches thematisiert. Der Einsatz und der Vorteil von Memristoren für den Aufbau von künstlichen Neuronalen Netzen wird  ebenfalls vorgstellt.

       

  • 24.01.2020
    • ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis
    • Prof. Dr. Jürgen Teich, Universität Erlangen-Nürnberg
       
    • With the ever increasing amount of data in recent years and the fact that data processing has become a major electric power consumer, the need for energy efficient data processing becomes more and more important every day. FPGAs can provide a mean to do energy efficient data processing due to custom high-speed circuits implementing the data processing directly in hardware. But that's not all. While some "hot" data is stored in modern in-memory systems, almost all data is also stored onto non-volatile storage.
       
      This talk discusses the opportunities and challenges of FPGA-based data processing and presents our ReProVide-Units which behave like FPGA-accelerated Network-attached Storage. Using dynamic partial reconfiguration, FPGAs could combine both, the performance of customized processing circuits and the flexibility to change the behaviors within milliseconds.