Reconfigurable and Embedded Systems
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FPGA based Systems
FPGA based platforms are a flexible and powerful way to implement a broad range of "Embedded Systems", utilizing different processor cores. Besisdes vendor specific solutions (like Xilinx MCS or MicroBlaze) the ARM-based processor cores are attractive candidates, ranging from the synthesizable Cortex-M0 core (50MHz) up to the Cortex-A9 dual-core hard-IPs (800MHz). FPGA Coprocessors employ a similar architectur. However in contrast to peripheral style functions the FPGA handles a significant or even the dominating portion of the overall functionality.
DSSC is a 2D-megapixel detector to be used at the XFEL facility at DESY, Hamburg. The detecor readout requires complex, FPGA-based readout electronics which has been developed by the research group. An I/O module located close to the detector receives the data from 16-detector ASICs - according to 1/16 of the detector - each over a 400 Mbit/s differential lines and combines them into four high-speed serial channels (3 Gbit/s). Due to lack of return lines at this point a protocol with forward error correction (FEC) has to be used. These high-speed data are received in a remote DAQ module and converted to 10Gb Ethernet UDP. This module is also responsible for communication with the global clock and control system and for the configuration of the sub-detector. In a separate train-builder unit, the 16 UDP channels are combined into full images and sent to the PC farm of the DAQ system.
This project is funded by the European XFEL
As part of the ATLAS upgrade program the pixel detector has very recently been equipped with an additional detector layer (IBL). The necessary off-detector readout electronics is connected via optical links and has to be largely compatible with existing hardware. With current FPGAs technology (Xilinx Virtex-5 and Spartan-6) almost all previously discrete functions can be integrated into FPGAs, simplifying the design significantly. In addition to the specific requirements of the optical channel connections - individual control of the mark-space ratio - a hybrid implementation of the calibration is investigated for IBL, which will replace the existing DSP-based solution. A fast FPGA processing unit builds histograms at full input speed, which are then analyzed on a host computer.
Research group activities are the development of the BOC (back-of-crate-card), the development of the FPGA-based histogramming running on the ROD (read-out-driver), the companion module to the BOC, and the development of major portions of the figh-level calibration algorithms running on a small server farm.
This project is funded by the BMBF.
At the LHC bunches of protons are brought to collision at a rate of 40MHz, the resulting interaction rate is in the range of 1GHz. The ATLAS experiment employs several sub-detectors with a total of approximately 100 million data channels for the signal acquisition. Electronics located close to the detector filters from the entire data volume events of about 1MB in size at a rate of 100kHz and sents them over 1,600 optical channels to the DAQ system. The nominal bandwidth per channel amounts to 160MB/s. A two-stage trigger system evaluates each event, first of approximately 10% of the channels. Based on this preliminary decision approximately 3% of the complete events will be analysed subsequently. The accepted events are stored at an average rate of 200Hz. This trigger concept requires an intelligent buffer that bridges the processing time of the first stage and can provide data on request. This intermediate buffer is realised in ATLAS via the Read-Out System (ROS) which consists of 160 PCs with 4 ROBIN cards each.
This project has been funded by the BMBF